While many types of integrated circuits may be designed to operate with a single internal voltage, it is often desirable to provide an integrated circuit (IC) including devices (e.g., transistors as well as passive circuit elements) that operate at two or more different voltage levels. Examples of such ICs include a Non-Volatile Memories (NVM) and an IC including a NVM or a flash macro, such as a micro-controller, microprocessor or programmable system on a chip (PSOC). Such a circuit typically includes low-voltage metal-on-semiconductor (LV_MOS) transistors used in logic and/or switching applications and designed to operate at a voltage of less than from about 2.5 to about 3.3 volts (V), and other high-voltage metal-on-semiconductor (HV_MOS) transistors used in NVM applications such as in input/output (I/O) cells or drivers, and typically designed to operate at voltages of about 9V or greater.
A conventional approach to integrating a HV_MOS transistor into such circuit, illustrated in FIG. 1, includes introducing a thick gate oxide for the HV_MOS transistor. Referring to FIG. 1, the circuit 100 includes a LV_MOS transistor 102 formed in a first region of a substrate 104 and a HV_MOS transistor 106 formed in a second region of the substrate. Typically, the first region of the substrate 104 is separated from the second region by an isolation structure, such as a shallow-trench-isolation (STI 108). Both the LV_MOS transistor 102 and the HV_MOS transistor 106 include source (S) and drain (D) diffusion regions 110, separated by a channel 112, a gate 114 overlying the channel, and a gate oxide (such as gate oxide 116 for the LV_MOS transistor and gate oxide 118 for the HV_MOS transistor), insulating the gate from the channel. The main difference between the LV_MOS transistor 102 and the HV_MOS transistor 106, other than that a low voltage is applied to the S/D diffusion regions 110 of the LV_MOS transistor while a high voltage is applied to the S/D diffusion regions of the HV_MOS transistor, is that the gate oxide 118 for the HV_MOS transistor is much thicker, typically 1.5 to 3 times thicker than the gate oxide 116 for the LV_MOS transistor.
Another approach to integrating a HV_MOS transistor into such circuit, illustrated in FIG. 2 includes introducing a drain-extended metal-on-semiconductor (DE_MOS) transistor 200 having a reduced surface effect (RESURF) architecture. Referring to FIG. 2, a RESURF-type DE_MOS 200 typically includes in addition to a source diffusion region 202, a channel 204, a gate oxide 206, a gate 208 and a RESURF-type drain extension 210 formed in the substrate 212. The RESURF-type drain extension 210 is asymmetric with respect to the source diffusion region 202 giving the RESURF-type DE_MOS 200 a larger drain region, and adding a STI 214 between a drain HV contact 216 and the channel 204. In addition, the RESURF-type drain extension 210 is typically more lightly doped than the drain diffusion region 110 of a conventional HV_MOS transistor 106, such as that described above. Increasing the size of the RESURF-type drain extension 210, adding the STI 214 and the light doping, all serve to increase a device breakdown voltage of the DE_MOS transistor 200. Thus, the gate oxide 206 of the DE_MOS transistor 200, although often thicker than that of a LV_MOS formed elsewhere in the same circuit, is typically not as thick as the HV_MOS transistor 106 described above.
The above solutions, while an improvement over previous approaches to integrating HV and LV devices in the same circuit are not wholly satisfactory for a number of reasons including the fact that they significantly increase the number of process steps and/or device footprint. In particular, both of the above approaches require a thicker gate oxide, which it typically takes 3-5 additional mask layers to introduce in to an existing MOS process flow. These additional mask layers significantly increase production costs and time while decreasing a yield of working circuits. Moreover, the introduction of these additional mask layers is not compatible with logic/mixed mode process technologies at foundries producing 130 nm technology nodes and below, which typically require a low thermal budget and limited number of wet processing steps. Finally, with regard to the RESURF-type DE_MOS transistor 200 it is noted the inclusion of the STI 214 within the RESURF-type drain extension 210 greatly increases the footprint of the device, making this approach unsuitable for applications in which the HV_MOS is part of circuit having tight critical dimension to space (CD/space) design rules, i.e., 0.47/1.2 μm or less, making it very difficult to use these devices in pitched circuits such as an I/O cells or drivers of a NVM.